1. Field of the Invention
The present invention is related to the field of semiconductor memory devices and, more specifically, to a flash memory device with a page buffer circuit having dual registers.
2. Description of the Related Art
The recent trends in semiconductor memory devices are for high integration, large capacity, and to support systems operating at high speeds. These trends are for both volatile memories (e.g., DRAM and SRAM) and non-volatile memories (e.g., flash memories).
Flash memories are generally subdivided into NOR-type flash memories and NAND-type flash memories. The NOR-type flash memories are used in applications necessary for reading information of a low volume at a high speed non-sequentially, while the NAND-type flash memories are used in applications necessary for reading information sequentially.
Flash memory devices use memory cells to store data. The memory cells include cell transistors. Each cell transistor has a control electrode and a floating gate. Since the flash memory device stores information using tunneling via an insulation film, it takes some time to store information.
In order to store information of a large volume in a short time, the NAND-type flash memory uses a register, which is also known as a page buffer circuit. Large volumes of data are supplied externally, for quick storing in the storage region. They are first stored in the register, and from there in the memory cells.
In the case of a conventional NAND-type flash memory, the magnitude of a page of data does not exceed 512 bytes. If it is assumed that a program time (or information storing time) of a NAND-type flash memory is about 200 to 500 microseconds, and 1-byte of data is loaded on the page buffer circuit from the exterior in a period of 100 nanoseconds, it takes about 50 microseconds to load 512-byte information in the page buffer circuit.
FIG. 1 shows a specific example in the prior art. FIG. 1 of the instant document is from U.S. Pat. No. 5,831,900 (that document's FIG. 7). Additional reference numerals have been added for the present discussion.
The device of FIG. 1 teaches that data are loaded to a latch 30 from a data line IO, after page buffers 20-i are reset by the surrounding circuitry. The data loaded to the latch are programmed to the memory cells 2-1, 2-2, 2-3, through a transistor Q4 (often by receiving an appropriate program command signal). This programming procedure is normally used to program NAND flash memories.
This procedure, however, has a limitation. In this program operation, if data is to be loaded to latch 30, it will have to wait until the data that was previously loaded finish programming in the previous program cycle. As it was described above, data loading to latch 30 progresses by byte units (e.g. 8 bit). So, it takes a long time for data to load to a page of as many as 2048 bytes. This is because latch 30 continues to store data until the information of the register is stored in the appropriate corresponding memory cells.
Another problem in the prior art is the copy back problem. Sometimes, a copy operation needs to be performed from a first page to a second page of data. If it is desired to perform the copy operation after the data of the memory cells in first page is latched to the latch circuit 30 through transistor Q7, then the latched data is programmed to the second page through the transistor Q4. In that case, programmed data copied to the second page are reversed, because of the latch circuit. In other words, 1 has become 0, and 0 has become 1. This problem is addressed in the prior art by providing flag cells to the memory cell array, and updating their value depending on whether the data has been inverted or not.
FIG. 2 shows a specific example of this problem in the prior art. FIG. 2 of the present document is from U.S. Pat. No. 5,996,041 (that document's FIG. 8 and FIG. 9). Additional reference numerals have been added for the present discussion.
In FIG. 2, copy back functions are shown. Data in the first page within the memory cell array is loaded to a page buffer. After that, the data is copied to another place in the array, but in inverted form. The bit to the right is the flag cell, to indicate that this data is in inverted form.
The prior art is limited as to how large the memory devices can become. For example, if it is assumed that the page buffer circuit can temporarily store 2048-byte information, it takes about 200 microseconds to load the 2048-byte of information when 1-byte information is loaded on a page buffer circuit by a period of 100 nanoseconds. Therefore the loading time is nearly similar to the information-storing time (or the program time) of 200 to 500 microseconds. Accordingly, the information-storing characteristic of the NAND-type flash memory is seriously affected by the loading time.
As integration of NAND-type flash memory increases, data must be processed in larger and larger volumes, as compared to the conventional flash memory. And it must be processed without deterioration in the information-storing characteristic.
The parent application's disclosure is briefly summarized in FIGS. 22 and 23 of the present application. As shown in FIGS. 22 and 23, a page buffer includes two registers including latches. The first register has a first latch LATCH 1 and the second register has a second latch LATCH 2. The detailed description of this structure is explained in parent U.S. patent application Ser. No. 10/013,191. As shown in FIG. 22, data to be programmed is loaded to the node N4 in LATCH 1 via the Data Line during phase F1. Next the data is transferred (or dumped) from mode N4 in LATCH 1 to the node N3 of the LATCH 2 during phase F2. According to the data state of the node N3, the data is programmed to the first page of the memory cell array, during a program phase F3 in FIG. 23. If the data of the node N3 is “0” (ground level and program state), then the memory cells are programmed. If on the other hand the data of the node N3 is “1” (Vcc level and program inhibit state), then the memory cells are not programmed. Note that a page includes a group of memory cells that are controlled by one word line.
After programming, the memory cells of the page must be checked to determine whether the memory cells have been successfully programmed. This checking procedure is referred to herein as “program verify read”, phase F4 of FIG. 23. In the program verify read procedure, if the cell to be programmed is not programmed, the state of node N3 is reset to “0” and if the cell to be programmed is programmed, the state of node N3 is reset to “1”. The cells that are not programmed must be reprogrammed according to the above program procedure.
If all of the cells are programmed, the node N3 is set to “1” during phase F5. This concludes the procedure for the first page of the memory cell array.
During the program procedure of the first page of the memory cell array, the data of the second page are simultaneously loaded to the node N4 in the LATCH 1. As a result, two procedures are carried out concurrently in a given page buffer.
U.S. Pat. No. 6,031,760 entitled SEMICONDUCTOR MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME describes in connection with FIG. 5 thereof a prior art single-latch memory device that is typical of conventional memory devices. The described circuit has a single sense amplifier S/A that includes only a single latch circuit LT.